Observed Signal · Jan 1, 2026 · Technical Release · Source: SemiAnalysis · Impact: 4/5 · Sentiment: Positive
Co‑Packaged Optics (CPO) Arrives for Datacenter Interconnect
SemiAnalysis presents an in‑depth technical and commercial analysis of co‑packaged optics (CPO) for datacenter networking, arguing CPO will be commercially relevant starting in 2025 and will be the primary scaling path for scale‑up AI interconnects later this decade. The report compares CPO to pluggable transceivers and co‑packaged copper, quantifies power and TCO tradeoffs (including published Meta and SemiAnalysis estimates showing big per‑800G power reductions), and reviews product roadmaps and early deployments from Nvidia and Broadcom. It examines critical enabling technologies and supply‑chain elements (optical engines, modulators, laser sources, fiber attach units, TSMC COUPE packaging), reliability and serviceability concerns, and vendor strategies. The piece concludes scale‑up networking is the “killer” CPO use case, while scale‑out adoption will initially be limited until manufacturing, standards, and field reliability mature.
CPO shifts datacenter interconnect architecture and materially affects AI compute scaling, power and TCO; major vendors (Nvidia, Broadcom, TSMC) are shipping or committing roadmaps, making this an infrastructure development with broad industry impact.
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Key Takeaways & Evidence Grounding
- SemiAnalysis expects tangible deployment‑ready CPO products starting in 2025 and broader scale‑up adoption later this decade.
- Nvidia announced CPO scale‑out switches at GTC 2025 (Quantum X800‑Q3450) and plans Spectrum‑X Photonics family in 2026; Broadcom has shipped early CPO systems (Humboldt, Bailly).
- CPO optical engines + external laser sources are estimated to consume ~4–5W per 800G vs ~15–17W for an 800G DSP transceiver (approx. 65–73% reduction per 800G by SemiAnalysis/Meta data).
- TSMC’s COUPE integration (SoIC/hybrid bonding + PIC/EIC flow) is emerging as the preferred high‑volume integration path for optical engines.
- Meta’s ECOC tests reported improved CPO MTBF vs pluggables (no uncorrectable codewords up to 4M 400G port‑hours and higher MTBF for CPO in their study), but the report calls for much larger field trials.
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Co‑Packaged Optics (CPO) Primer
The article explains co‑packaged optics (CPO), a datacenter trend that integrates the optical engine onto or into the switch package to eliminate long copper traces between switch ASICs and transceivers. By moving modulation to silicon photonics and using external continuous‑wave (CW) lasers, CPO reduces the need for DSPs and high‑power SerDes, cutting power and potentially improving reliability and latency. The piece contrasts CPO with pluggable transceivers and intermediate approaches (near‑package optics), highlights manufacturing and serviceability tradeoffs, and notes industry momentum — Nvidia plans CPO shipments in 2026, Broadcom and Marvell are active in early programs, and value is shifting toward silicon photonics, CW laser supply, and advanced packaging while reducing demand for pluggable DSP modules.
VCSELs and the 200G-per-Lane Wall in AI Datacenters
This technical analysis (May 6, 2026) explains why VCSELs (vertical-cavity surface-emitting lasers) have dominated short-reach datacenter optics for decades and why the industry's move from 100G to 200G per lane is creating supply-chain and technical challenges. Coherent said it recently demonstrated three different 1.6T transceiver implementations—silicon photonics (SiPh), EMLs, and VCSELs—signaling platform hedging as hyperscalers push from 800G to 1.6T (with 3.2T on the horizon). The article traces VCSEL history (Honeywell research in 1993; first commercial product 1996), the acquisition chain through Finisar and II‑VI/Coherent, and highlights VCSELs' mature, high-volume supply chain driven by consumer uses (e.g., smartphone dot projectors). The piece frames the 200G-per-lane jump as an inflection that could break VCSEL's short-reach advantage and reshape optical interconnect market dynamics.
Chipmakers Turn to Photonics to Fix AI Bottleneck
Photonics — using light instead of electrical signals — is emerging as a potential solution to the data-transfer bottleneck between AI chips, servers and memory. Nvidia has announced multi‑billion dollar investments into photonics developers, including $2 billion since March to Lumentum, Coherent and Marvell, a $500 million investment into Corning, and participation in Ayer Labs’ $500 million Series E. Proponents say optical interconnects and silicon photonics can materially speed GPU‑to‑GPU and rack‑level communication and reduce energy costs. Analysts warn large challenges remain: manufacturing and supply‑chain ramping, and the need to redesign product roadmaps — which could take another one or two product generations before broad adoption. The article was published on 2026-05-29.
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