Observed Signal · Jul 2, 2026 · Technical Release · Source: t3n · Impact: 4/5 · Sentiment: Positive
IBM's Nanostack Chip Aims to Extend Moore’s Law
IBM announced a prototype 'Nanostack' chip that vertically stacks transistors to increase density and efficiency. The prototype reportedly contains about 100 billion transistors on a fingernail-sized area, roughly doubling the transistor density compared with IBM’s 2021 leading technology. Nanostack uses a two-layer complementary field-effect transistor (CFET) vertical stacking approach with three nanosheet channels per transistor; IBM markets the generation as 'Sub‑Nanometer' or '0.7 Nanometer' (a label rather than a physical measurement). IBM says chips using the approach can deliver up to 50% more work and up to 70% better energy efficiency versus its prior architecture. The report notes other major manufacturers (Intel, Samsung, TSMC) and research lab Imec are also working on CFET concepts, while manufacturing yield, thermal-budget limits and layer-alignment remain key challenges for mass production.
A major IBM prototype that materially increases transistor density and energy efficiency could influence future compute capacity (data centers, AI processors) and semiconductor roadmaps; however, practical manufacturing and yield challenges remain before broad industry impact.
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Key Takeaways & Evidence Grounding
- IBM developed a prototype 'Nanostack' chip containing ~100 billion transistors on an area the size of a fingernail.
- IBM says the new design roughly doubles transistor density versus its 2021 leading technology and claims up to 50% more performance and up to 70% better energy efficiency for chips using the approach.
- Nanostack stacks transistors vertically in two layers using a CFET (complementary field-effect transistor) architecture and three nanosheet channels per transistor.
- Major semiconductor players and research organisations — Intel, Samsung, TSMC and Imec — are also working on CFET or similar vertical-stacking approaches.
- Manufacturing challenges highlighted include higher defect-driven yield loss for multi-layer chips and a strict thermal budget (processes must stay below ~400°C).
Connected Companies & Entities
7 Entities mapped“IBM has developed a new prototype chip with around 100 billion transistors on an area the size of a fingernail....”
“The largest chipmakers — Intel, Samsung and TSMC — and the research lab Imec in Belgium are also working on CFETs....”
“The largest chipmakers — Intel, Samsung and TSMC — and the research lab Imec in Belgium are also working on CFETs....”
“CFETs like IBM's Nanostack stand in contrast to other two-tier chip approaches such as AMD's 3D-V-Cache....”
“CFETs like IBM's Nanostack stand in contrast to other two-tier chip approaches such as the upcoming LogicFolding technology from Huawei....”
“The article includes an editorial caption: 'Insight into ASML's lithography machines.'...”
“External content from TargetVideo GmbH supplements the editorial offering on t3n.de, according to the site note....”
Ontology Mapping & Concepts
Related Market Signals & Shifts
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IBM's Nanostack Stacks Transistors for Efficient AI Chips
IBM announced a prototype chip called "Nanostack" that vertically stacks transistor layers to increase density and efficiency. The prototype contains about 100 billion transistors on a fingernail-sized area — roughly double the transistor density compared with IBM's 2021 leading design. Nanostack uses a two-layer complementary FET (CFET) vertical-stacking approach and three-nanosheet channels; IBM claims up to 50% more work per clock and up to 70% better energy efficiency in some comparisons. IBM says it will collaborate with semiconductor manufacturers to produce chips and expects Nanostacking could reach datacenter deployments within a decade. Academic and industry observers (including TechInsights, University of Illinois researchers, and others) called the work significant while noting manufacturing challenges such as yield, thermal budgets, and alignment across layers.
IBM links modular cryogenic systems for fault-tolerant quantum computing
IBM reports a technical milestone after connecting two modular cryogenic systems and jointly cooling them to below 15 millikelvin. The modules, each more than 2.4 meters in height and width, are designed to be combined into larger systems and house increased wiring capacity to support many chip connections. IBM described an L-Coupler technology that enables direct data exchange between separate quantum chips; the company plans to use this approach to build a machine with at least 1,000 programmable qubits by 2027 and to integrate first Nighthawk processors into the new cryomodules this year. The modular cooling architecture is positioned as a key step toward IBM’s stated goal of delivering a fault-tolerant quantum computer (IBM Quantum Starling) by 2029.
Intel Ships Backside Power Delivery; 30% IR Drop Cut
The article explains backside power delivery (BSPDN), a chip architecture that moves power wiring to the wafer backside using nano-TSVs and a backside metallized power grid. Intel implemented BSPDN as PowerVia in its 18A process and began mass production in the Panther Lake family in early 2026, citing ~30% IR‑drop reduction, ~6% clock uplift and 5–10% standard‑cell utilization gains. The piece describes the manufacturing steps (wafer thinning, carrier bonding, nTSV formation, backside patterning), cost and yield tradeoffs, and competitive timing: TSMC plans a Super Power Rail for A16 (H2 2026 target) and Samsung targets SF2Z in 2027. Implications for AI accelerators include improved power efficiency, higher logic density and better thermal behavior; consumer GPUs are unlikely to see BSPDN widely until A16/N2 follow-on generations (2028+).
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